This invention relates to a display device, and more particularly to a display device such as a fluorescent display device or the like which is adapted to display characters, figures or the like.
A fluorescent display device which is one example of a conventional display device is generally constructed as shown in FIG. 3.
A fluorescent display tube (VFD) 309 which constitutes a display section of the fluorescent display device includes a plurality of control electrodes and anodes arranged so as to intersect each other, which cooperate together to form a matrix-like image plane for display. The control electrodes and anodes are adapted to be driven by a control electrode drive circuit 305 and an anode drive circuit 308, respectively, resulting in any desired characters and/or figures being displayed on the image plane.
A counter 301 is arranged so as to count a reverse signal HSYNC of a horizontal synchronous signal in response to the leading of a reverse signal VSYNC of a vertical synchronous signal to output a counting signal corresponding to a value counted by the counter. Data are written in addresses of a ROM 303 and data in the address to which the counting signal is input from the counter 301 are supplied to the control electrode drive circuit 305. For example, supposing that an output data at one of output terminals of the ROM 303 is 1010, a repetitive signal of high and low levels is obtained. Output signals of the ROM 303 include a grid clock signal, a clock effective signal for determining time at which the clock is handled to be effective and a grid clear signal for determining time at which a display section drive signal is output from the control electrode drive circuit 305. A drive signal is formed in the control electrode drive circuit 305 depending upon the grid clock signal from the ROM 303 and supplied to the VFD 309 in response to the clear signal from the ROM 303.
The counter 303 starts counting of the clock signal in response to the leading of the HSYNC. A ROM 304 outputs data for a corresponding address in response to the counting signal from the counter 302. More specifically, a serial/parallel (S/P) conversion circuit 306 has supplied thereto an anode clock signal and a latch circuit 307 has supplied thereto a latch signal, and an anode clear signal for outputting a drive signal to an anode corresponding to a signal latched to the latch signal 307 is supplied to the anode drive circuit 308.
The S/P conversion circuit 306 takes in a display signal Vs in synchronism with the anode clock signal to store therein data corresponding in number to the anodes and then supplies the signal to the latch circuit 307 in the form of a parallel signal. The latch circuit 307 latches the so-supplied parallel signal in synchronism with the latch signal, resulting in the latched parallel signal being output from the anode drive circuit 308 to the VFD 309 in the form of a drive signal of a predetermined voltage in response to the anode clear signal.
In the VFD 309, the respective two control electrodes adjacent to each other are scanned in turn while being shifted one by one and synchronously the drive signal is supplied to the anodes, resulting in desired display being exhibited corresponding to the display signal.
When the above-described display device is used for a personal computer or the like, it is often experienced that the clock signal, VSYNC, HSYNC and display signal are different in timing from each other depending upon the type of the personal computer. In the conventional display device, a display position is fixed, so that the difference in timing between the signals causes problems such as a failure in display at the central position on the image plane, a display defect and the like. In order to carry out display at a suitable position on an image plane, it is conventionally required to replace each of the ROMs 303 and 304 with another ROM.